Wiring substrate device

ABSTRACT

A wiring substrate device includes a wiring substrate, a plurality of terminals each of which is provided upright on the wiring substrate and has a lower end, an upper end and a narrowed part between the lower end and the upper end, and a plurality of solders each of which has a melting point lower than the terminals and covers a surface of the corresponding terminal.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority from Japanese Patent ApplicationNo. 2017-183549 filed on Sep. 25, 2017, the entire content of which isincorporated herein by reference.

BACKGROUND Technical Field

The present disclosure relates to a wiring substrate device.

Related Art

There are various types of terminals for connecting components such as asemiconductor device to a wiring substrate. Among them, solder bumpshave been widely used because they are melted by reflow and thesemiconductor device can be thus easily mounted on the wiring substrate.

However, when the solder bumps are melted by the reflow, the adjacentsolder bumps are contacted to each other, so that the solder bumps maybe electrically shorted. Furthermore, the melted solder bumps aresquashed, so that an interval between the wiring substrate and thesemiconductor device is reduced and the semiconductor device may be thuscontacted to the wiring substrate, in some cases.

Patent Document 1: JP-A-H11-103160

SUMMARY

Exemplary embodiments of the present invention provides a wiringsubstrate device capable of keeping an interval between a wiringsubstrate and a component and suppressing electrical short of terminalsadjacent to each other.

A wiring substrate device according to an exemplary embodimentcomprises:

a wiring substrate;

a plurality of terminals each of which is provided upright on the wiringsubstrate and has a lower end, an upper end and a narrowed part betweenthe lower end and the upper end; and

a plurality of solders each of which has a melting point lower than theterminals and covers a surface of the corresponding terminal.

According to one aspect, since the melted solder is accumulated at thenarrowed part of the terminal, it is possible to prevent the meltedsolder from spreading in a horizontal direction of the substrate and tosuppress electrical short of the adjacent terminals via the solder.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an entire sectional view of a wiring substrate used forexamination.

FIGS. 2A and 2B are enlarged sectional views depicting a state where awiring substrate device used for examination is being manufactured (1thereof).

FIGS. 3A and 3B are enlarged sectional views depicting a state where thewiring substrate device used for examination is being manufactured (2thereof).

FIG. 4 is an enlarged sectional view for illustrating a problem of thewiring substrate device used for examination (1 thereof).

FIG. 5 is an enlarged sectional view for illustrating a problem of thewiring substrate device used for examination (2 thereof).

FIG. 6 is an enlarged sectional view for illustrating a problem of thewiring substrate device used for examination (3 thereof).

FIG. 7A is a top view of a terminal relating to a first exemplaryembodiment, and FIG. 7B is a sectional view taken along a line I-I ofFIG. 7A.

FIG. 8 is a sectional view of the terminal having a solder provided on asurface thereof in accordance with the first exemplary embodiment.

FIG. 9A is a sectional view depicting a manufacturing method of theterminal relating to the first exemplary embodiment, and FIG. 9B is apartial sectional side view taken along a line II-II of FIG. 9A.

FIGS. 10A and 10B are enlarged sectional views depicting a state where awiring substrate device in accordance with the first exemplaryembodiment is being manufactured (1 thereof).

FIGS. 11A and 11B are enlarged sectional views depicting a state wherethe wiring substrate device in accordance with the first exemplaryembodiment is being manufactured (2 thereof).

FIG. 12 is an entire sectional view of the wiring substrate device inaccordance with the first exemplary embodiment.

FIG. 13 is an enlarged sectional view for illustrating an effect to beaccomplished in the first exemplary embodiment (1 thereof).

FIG. 14 is an enlarged sectional view for illustrating an effect to beaccomplished in the first exemplary embodiment (2 thereof).

FIG. 15A is a top view of a terminal relating to a second exemplaryembodiment, and FIG. 15B is a side view of the terminal.

FIG. 16A is a top view depicting a case where the terminal relating tothe second exemplary embodiment is provided with a solder, and FIG. 16Bis a sectional view taken along a line III-III of FIG. 16A.

FIG. 17A is a sectional view depicting a manufacturing method of theterminal relating to the second exemplary embodiment, and FIG. 17B is apartial sectional side view taken along a line IV-IV of FIG. 17A.

FIG. 18 is a partial sectional side view of a wiring substrate device inaccordance with the second exemplary embodiment.

FIG. 19A is a top view of a terminal relating to a third exemplaryembodiment, and FIG. 19B is a sectional view taken along a line V-V ofFIG. 19A.

FIG. 20 is a sectional view depicting a case where the terminal of thethird exemplary embodiment is provided with a solder.

FIG. 21A is a sectional view depicting a manufacturing method of theterminal relating to the third exemplary embodiment, and FIG. 21B is apartial sectional side view taken along a line VI-VI of FIG. 21A.

FIG. 22 is an enlarged sectional view of a wiring substrate device ofthe third exemplary embodiment.

FIG. 23 is a sectional view for illustrating an effect to beaccomplished in the third exemplary embodiment (1 thereof).

FIG. 24 is a sectional view for illustrating an effect to beaccomplished in the third exemplary embodiment (2 thereof).

FIG. 25 is an enlarged sectional view of a wiring substrate device inaccordance with a fourth exemplary embodiment.

DETAILED DESCRIPTION

Before describing exemplary embodiments, the matters that have beenexamined by the inventor are described.

FIG. 1 is an entire sectional view of a wiring substrate used forexamination.

The wiring substrate 1 is a multi-layered wiring substrate, and isconfigured by stacking alternately insulation layers 6 and wirings 4, 7on both surfaces of a core base material 2.

The core base material 2 is a glass epoxy substrate in which epoxy resinis impregnated in glass cloth, and has a plurality of through-holes 2 a.The through-hole 2 a and opening ends thereof are formed with copperplated films, so that a through-electrode 3 is provided in thethrough-hole 2 a and the wiring 4 is provided on the core base material2 around the through-electrode 3.

Also, the insulation layer 6 is a resin layer such as a phenol resin, apolyimide resin and the like. The resin layer 6 is formed with a viahole 6 a reaching the wiring 4 by laser processing or the like, and thewiring 7 is formed in the via hole 6 a and on the insulation layer 6around the via hole by copper plating.

An upper main surface of both main surfaces of the wiring substrate 1 isformed with a first solder resist layer 11. The first solder resistlayer 11 is provided with first openings 11 a exposing the wiring 7 ofthe uppermost layer. A surface of the wiring 7 in the first opening 11 ais formed with a first diffusion prevention layer 12.

The first diffusion prevention layer 12 is a metal layer for preventinga solder, which is to be formed later on the first diffusion preventionlayer, from diffusing into the wiring 7, and is also referred to as aUBM (Under Barrier Metal). In this example, a nickel layer, a palladiumlayer and a gold layer are formed in corresponding order, as the firstdiffusion prevention layer 12.

In the meantime, a lower main surface of both the main surfaces of thewiring substrate 1 is formed with a second solder resist layer 13. Thesecond solder resist layer 13 is formed with second openings 13 aexposing the wiring 7 of the lowest layer. A surface of the wiring 7 inthe second opening 13 a is formed with a second diffusion preventionlayer 14.

Like the first diffusion prevention layer 12, the second diffusionprevention layer 14 is a stacked film formed by stacking a nickel layer,a palladium layer and a gold layer in corresponding order.

In this example, a semiconductor device is mounted on the wiringsubstrate 1, as follows.

FIGS. 2A to 3B are enlarged sectional views depicting states where awiring substrate device using the wiring substrate 1 is beingmanufactured.

First, as shown in FIG. 2A, a terminal 16 is erected in the firstopening 11 a.

The terminal 16 has a column shape obtained by cutting a nickel wire rodinto a predetermined length, and a solder 17 is formed on a surfacethereof by barrel plating,

Subsequently, as shown in FIG. 2B, the solder 17 is reflowed and melted,so that the terminal 16 is joined to the wiring 7 via the solder 17 andthe first diffusion prevention layer 12. Upon the reflow, the solder 17is formed to have a schematically spherical shape by surface tension.

By the above processes, a basic structure of a wiring substrate device25 relating to this example is completed.

Then, the wiring substrate device 25 is subjected to a process ofmounting thereon a semiconductor device.

First, as shown in FIG. 3A, a semiconductor device 2.0 having aplurality of electrodes 21 is prepared, and the electrodes 21 and theterminals 16 are positionally aligned. Although the electrode 21 is notparticularly limited, a copper post is formed as the electrode 21, inthis example.

Then, as shown in FIG. 3B, while pressing the semiconductor device 20toward the wiring substrate 1, the solders 17 are reflowed and melted,so that the terminals 16 and the electrodes 21 are interconnected viathe solders 17.

During the reflow, a heating temperature is set to a temperature higherthan a melting point of the solder 17 and lower than a melting point ofthe terminal 16. For this reason, the solder 17 is melted by the reflowbut the terminal 16 keeps the column shape without being melted.

By the above processes, the basic processes of this example are over.

According to the wiring substrate device 25, since the nickel terminal16 having the melting point higher than the solder 17 is adopted, theterminal 16 is not melted even when the solder 17 is reflowed in theprocess of FIG. 3B. Thereby, even when the semiconductor device 20 ispressed upon the reflow, the terminal 16 is not squashed, Accordingly,an interval between the first wiring substrate 1 and the semiconductordevice 20 is kept by the terminals 16 and it is possible to prevent thesemiconductor device 20 from contacting the first wiring substrate 1.

However, following problems may occur in the wiring substrate device 25.

FIGS. 4 to 6 are enlarged sectional views for illustrating the problems.

In an example of FIG. 4, when the solders 17 are reflowed in the processof FIG. 2B or 3B, the solders 17 are spread in a horizontal directiondue to the surface tension, so that the adjacent terminals 16 areelectrically shorted via the solders 17.

In order to avoid the above problem, it is considered to reduce anamount of the solder 17 on the surface of the terminal 16. However,according to this method, an amount of the solder 16 is insufficient ata lower end 16 a and an upper end 16 b of the terminal 16, so thatjoining strength between the lower end 16 a and the wiring 7 and joiningstrength between the upper end 16 a and the electrode 21 may beinsufficient.

FIG. 5 is an enlarged sectional view depicting a case where heights ofthe plurality of electrodes 21 are not uniform due to a manufacturingerror.

In this case, the solder 17 is not contacted to the electrode 21 ofwhich height is low, so that the electrode 21 and the terminal 16corresponding to the electrode are not electrically connected to eachother.

FIG. 6 is an enlarged sectional view depicting a case where thesemiconductor device 20 is bent due to thermal expansion and the like.

In this case, a part of the electrodes 21 is detached from the terminal16 due to the bending of the semiconductor device 20, so that theterminal 16 and the electrode 21 cannot be connected to each other bythe solder 17.

In the below, each exemplary embodiment capable of avoiding the aboveproblems is described.

First Exemplary Embodiment

First, a terminal that is used in a first exemplary embodiment isdescribed.

FIG. 7A is a top view of the terminal, and FIG. 7B is a sectional viewtaken along a line I-I of FIG. 7A.

As shown in FIG. 7A, a terminal 30 has a circular shape, as seen fromabove.

Also, as shown in FIG. 7B, the terminal 30 has a lower end 30 a and anupper end 30 b, and a narrowed part 30 c having a width narrower thaneach of the lower end 30 a and the upper end 30 b is provided betweenthe lower and upper ends.

In this example, the narrowed part 30 c is provided with a narrowportion 30 d having a smallest width W₁, as seen from a cross sectionalview. A sectional shape of the terminal 30 is narrowed in a taperedshape from the lower end 30 a toward the narrow portion 30 d, and asectional shape of the terminal 30 is widened in a tapered shape fromthe narrow portion 30 d toward the upper end 30 b.

A size of the terminal 30 is not particularly limited. For example, aheight H of the terminal 30 is about 10 μm to 1000 μm, and a width W₂ ofeach of the lower end 30 a and the upper end 30 b is about 10 μm to 500μm. Also, the width W₁ of the narrow portion 30 d is about 5 μm to 495μm, and more preferably about 300 μm.

Also, a material of the terminal 30 is not particularly limited. Forexample, the terminal 30 may be formed of any one of nickel, copper,gold and aluminum.

In the first exemplary embodiment, a solder is provided on a surface ofthe terminal 30, as follows.

FIG. 8 is a sectional view of the terminal 30 having a solder 31provided on the surface thereof.

The solder 31 is formed to have a thickness of about 5 μm to 100 μm onthe entire surface of the terminal 30 by barrel plating, for example.

Also, a material of the solder 31 is not particularly limited inasmuchas it is a material having a melting point lower than the terminal 30.For example, tin or lead may be adopted.

Subsequently a manufacturing method of the terminal 30 is described.

FIG. 9A is a sectional view depicting a manufacturing method of theterminal 30. Also, FIG. 9B is a partial sectional side view taken alonga line II-II of FIG. 9A.

As shown in FIGS. 9A and 9B, in this example, jigs 33 are arranged aboveand below a linear nickel wire rod 30 x. The jig 33 is formed with aninclined surface 33 a corresponding to the narrowed part 30 c (refer toFIG. 7B). The wire rod 30 x is rotated and pinched several times by thejigs 33, so that the wire rod 30 x is processed into a tapered shape.

In the meantime, the wire rod 30 x may be processed into a tapered shapeby a rolling processing method or the like.

After processed into the tapered shape, the wire rod 30 x is cut into apredetermined length, so that the terminal 30 having the narrowed part30 c is obtained.

Subsequently, a wiring substrate device having the terminals 30 isdescribed with reference to a manufacturing method thereof.

FIGS. 10A to 11B are enlarged sectional views depicting states where awiring substrate device of the first exemplary embodiment is beingmanufactured. In FIGS. 10A to 11B, the same elements as those describedin FIGS. 1 to 3B are denoted with the same reference numerals as thosein FIGS. 1 to 3B and the descriptions thereof are omitted.

In the first exemplary embodiment, the terminal 30 is provided uprighton the wiring substrate 1, as follows.

First, as shown in FIG. 10A, the terminals 30 are erected in the firstopenings 11 a of the first solder resist layer 11 with the lower ends 30a being located downward.

Then, as shown in FIG. 10B, the solders 31 are reflowed and melted, sothat the terminals 30 are connected to the wiring 7 via the solders 31and the first diffusion prevention layers 12. During the reflow, aheating temperature is set to a temperature higher than the meltingpoint of the solder 31 and lower than the melting point of the terminal30, for example, about 100° C. to 400° C.

In the first exemplary embodiment, during the reflow, since the meltedsolder 31 is accumulated at the narrowed part 30 c by the surfacetension, it is possible to prevent the solder 31 from spreading in ahorizontal direction and to reduce a risk that the adjacent terminals 30will be electrically shorted by the solder 31.

In the meantime, as described above, since the heating temperature ofthe reflow is lower than the melting point of the terminal 30, theterminal 30 is not melted by the reflow.

By the above processes, a wiring substrate device 35 of the firstexemplary embodiment is completed. In this embodiment, as shown in FIG.8, the solder 31 is provided on the entire surface of the terminal 30.However, the solder 31 may not be provided on the lower end 30 a of theterminal 30 and the lower end 30 a of the terminal 30 may be in directcontact with the wiring 7 without the solder 31 and the first diffusionprevention layer 12.

In the wiring substrate device 35, the first solder resist layer 11 isformed on the wiring 7 around the terminal 30, and the terminal 30protrudes from the first solder resist layer 11.

Subsequently, a process of mounting a component such as a semiconductordevice on the terminal 30 of the wiring substrate device 35 isperformed.

First, as shown in FIG. 11A, a semiconductor device 20 having aplurality of electrodes 21 is prepared, and the electrodes 21 and theterminals 30 are positionally aligned. A type of the semiconductordevice 20 is not particularly limited. For example, a processor such asa CPU (Central Processing Unit) may be adopted as the semiconductordevice 20.

Also, like the example of FIG. 3A, the electrode 21 is a metal post suchas a copper post.

Then, as shown in FIG. 11B, the solders 31 are reflowed and melted whilepressing the semiconductor device 20 toward the wiring substrate 1, sothat the terminals 30 and the electrodes 21 are interconnected via thesolders 31.

During the reflow, the heating temperature is set to a temperaturehigher than the melting point of the solder 31 and lower than themelting point of the terminal 30, for example, about 100° C. to 400° C.For this reason, during the reflow, the terminals 30 are not melted andan interval between the wiring substrate 1 and the semiconductor device20 can be kept by the terminals 30 even when the semiconductor device 20is pressed toward the wiring substrate 1, so that the semiconductordevice 20 can be prevented from contacting the wiring substrate 1.

Furthermore, the melted solder 31 is accumulated at the narrowed part 30c of the terminal 30, so that the solder 31 does not spread in thehorizontal direction and it is thus possible to reduce a possibilitythat the adjacent terminals 30 will be electrically shorted due to thesolder 31.

In particular, like this example, the narrow portion 30 d is positionedabove an upper surface 11 x of the first solder resist layer 11, so thatit is possible to prevent the narrow portion 30 d from being screened bythe first solder resist layer 11. As a result, the more solder 31 can beaccumulated at the narrowed part 30 c, so that it is possible toeffectively suppress the solder 31 from spreading in the horizontaldirection.

Also, the narrow portion 30 d is exposed, so that the solder 31 can beaccumulated between the narrow portions 30 d, which are most distantfrom each other between the adjacent terminals 30. Accordingly, it ispossible to suppress the solder 31 from spreading in the horizontaldirection.

In this way, the basic processes of the first exemplary embodiment arecompleted.

FIG. 12 is an entire sectional view including the semiconductor device20.

In this example, after the semiconductor device 20 is mounted on thewiring substrate 1, as described above, an underfill resin 38 is filledbetween the wiring substrate 1 and the semiconductor device 20. Also, asolder bump functioning as an external connection terminal 39 is formedon the wiring 7 exposed from the second opening 13 a of the secondsolder resist layer 13.

In the meantime, the underfill resin 38 and the external connectionterminal 39 may be omitted if they are not necessary. This applies toeach exemplary embodiment to be described later, as well.

According to the first exemplary embodiment, the terminals 30 having themelting point higher than the solder 31 are arranged between the wiringsubstrate 1 and the semiconductor device 20. Thereby, even when thesolder 31 is reflowed, it is possible to keep the interval between thewiring substrate 1 and the semiconductor device 20 and to reduce acontact possibility of the wiring substrate 1 and the semiconductordevice 20.

In particular, when using the underfill resin 38, as shown in FIG. 12,the interval between the wiring substrate 1 and the semiconductor device20 is kept, so that the underfill resin 38 can be easily filledtherebetween.

Also, as shown in FIG. 11B, the terminal 30 is provided with thenarrowed part 30 c, so that it is possible to prevent the solder 31 fromspreading in the horizontal direction of the substrate and to reduce apossibility that the adjacent terminals 30 will be interconnected viathe solder 31.

Furthermore, since it is not necessary to reduce an amount of the solder31 so as to prevent the solder 31 from spreading in the horizontaldirection, a sufficient amount of the solder 31 is uniformly spread toeach of the lower end 30 a and the upper end 30 b of the terminal 30. Asa result, it is possible to sufficiently secure connection strengthbetween the terminal 30 and the wiring substrate 1 and connectionstrength between the terminal 30 and the semiconductor device 20 by thesolder 31, so that it is possible to maintain connection reliabilitybetween the wiring substrate 1 and the semiconductor device 20.

Also, according to the first exemplary embodiment, following effects canalso be accomplished.

FIGS. 13 and 14 are enlarged sectional views for illustrating effects tobe accomplished in the first exemplary embodiment.

FIG. 13 is a sectional view depicting a case where the heights of theplurality of electrodes 21 are not uniform due to a manufacturing error.

In this case, when the semiconductor device 20 is pressed in the processof FIG. 11B, the narrowed parts 30 c, which are mechanically weak, aresquashed, so that it is possible to absorb the non-uniformity of theheights of the respective electrodes 21 by the terminals 30. For thisreason, unlike the example of FIG. 5, it is possible to suppress asituation where a part of the plurality of terminals 30 is not connectedto the electrode 21, so that it is possible to suppress a yield of thewiring substrate device from being lowered.

FIG. 14 is a sectional view depicting a case where the semiconductordevice 20 is bent due to thermal expansion or the like.

In this case, when the semiconductor device 20 is pressed in the processof FIG. 11B, the terminal 30 is bent at the narrowed part 30 c, so thatthe upper end 30 b of the terminal 30 conforms to the bending of thesemiconductor device 20. Thereby, unlike the example of FIG. 6, it ispossible to connect each of the plurality of terminals 30 to theelectrode 21.

Second Exemplary Embodiment

In a second exemplary embodiment, an amount of the solder 31 to beaccumulated at the narrowed part 30 c is larger than the first exemplaryembodiment.

FIG. 15A is a top view of the terminal 30 of the second exemplaryembodiment, and FIG. 15B is a side view of the terminal 30.

Meanwhile, in FIGS. 15A and 15B, the same elements as those described inthe first exemplary embodiment are denoted with the same referencenumerals as those in the first exemplary embodiment and the descriptionsthereof are omitted.

As shown in FIGS. 15A and 15B, in the second exemplary embodiment, aside of the terminal 30 is formed with a plurality of grooves 30 gextending from the lower end 30 a to the upper end 30 b.

FIG. 16A is a top view depicting a case where the terminal 30 isprovided with the solder 31, and FIG. 16B is a sectional view takenalong a line III-III of FIG. 16A.

Like the first exemplary embodiment, the solder 31 is formed on thesurface of the terminal 30 by the barrel plating.

In particular, as shown in FIG. 16A, in the second exemplary embodiment,since a surface area of the side of the terminal 30 increases due to thegrooves 30 g, it is possible to provide the more solder 31 on theterminal 30, as compared to a configuration where the grooves 30 g arenot provided.

Subsequently, a manufacturing method of the terminal 30 is described.

FIG. 17A is a sectional view depicting a manufacturing method of theterminal 30 relating to the second exemplary embodiment. Also, FIG. 17Bis a partial sectional side view taken along a line IV-IV of FIG. 17A.

As shown in FIGS. 17A and 17B, also in the second exemplary embodiment,the wire rod 30 x is rotated and pinched several times by the pair ofjigs 33 and is thus formed with the narrowed part 30 c (refer to FIG.15B).

In the meantime, the wire rod 30 x may be processed into a tapered shapeby a rolling processing method or the like.

Also, as shown in FIG. 17B, the jig 33 is provided with a concavity andconvexity 33 b corresponding to the groove 30 g (refer to FIG. 15A), sothat it is possible to form the groove 30 g by transferring theconcavity and convexity 33 b to the wire rod 30 x.

FIG. 18 is a partial sectional side view of a wiring substrate device 35having the terminals 30 in accordance with the second exemplaryembodiment.

Meanwhile, in FIG. 18, the same elements as those described in the firstexemplary embodiment are denoted with the same reference numerals asthose in the first exemplary embodiment and the descriptions thereof areomitted.

The wiring substrate device 35 is manufactured by performing the sameprocesses as FIGS. 10A to 11B of the first exemplary embodiment, and hasa structure where the wiring substrate 1 and the semiconductor device 20are connected to each other by the terminals 30.

In the second exemplary embodiment, the grooves 30 g are formed, so thatit is possible to provide the more solder 31 on the surface of theterminal 30. Therefore, the solder 31 is difficult to be insufficient atthe lower end 30 a and the upper end 30 b of the terminal 30. As aresult, it is possible to sufficiently secure the connection strengthbetween the terminal 30 and the wiring substrate 1 and the connectionstrength between the terminal 30 and the semiconductor device 20 by thesolders 31.

Third Exemplary Embodiment

In a third exemplary embodiment, a shape of the narrowed part 30 c isdifferent from the first exemplary embodiment.

FIG. 19A is a top view of the terminal 30 relating to the thirdexemplary embodiment, and FIG. 19B is a sectional view taken along aline V-V of FIG. 19A.

Meanwhile, in FIGS. 19A and 19B, the same elements as those described inthe first exemplary embodiment are denoted with the same referencenumerals as those in the first exemplary embodiment and the descriptionsthereof are omitted.

As shown in FIGS. 19A and 19B, the terminal 30 of the third exemplaryembodiment has an upper plate 30 e including the upper end 30 b, a lowerplate 30 f including the lower end 30 a, and a column-shaped part 30 hconnecting the upper plate 30 e and the lower plate 30 f each other.

The column-shaped part 30 h is a part becoming the above-describednarrowed part 30 c, and has a width W₃ that is constant between thelower end 30 a and the upper end 30 b.

The width W3 is, for example, about 5 μm to 495 μm, and a height h ofthe column-shaped part 30 h is, for example, about 5 μm to 800 μm. Also,the width W₂ of each of the lower end 30 a and the upper end 30 b isabout 10 μm to 500 μm, like the first exemplary embodiment. A height Hof the terminal 30 is about 10 μm to 1000 μm.

FIG. 20 is a sectional view depicting a case where the terminal 30 isprovided with the solder 31.

Like the first exemplary embodiment and the second exemplary embodiment,the solder 31 is formed on the surface of the terminal 30 by the barrelplating.

Subsequently, a manufacturing method of the terminal 30 is described.

FIG. 21A is a sectional view depicting a manufacturing method of theterminal 30 relating to the third exemplary embodiment. Also, FIG. 21Bis a partial sectional side view taken along a line VI-VI of FIG. 21A.

As shown in FIGS. 21A and 21B, also in the third exemplary embodiment,the wire rod 30 x is rotated and pinched several times by the pair ofjigs 33 and is thus formed with the narrowed part 30 c (refer to FIG.19B).

In the meantime, the wire rod 30 x may be formed with the narrowed part30 c by a rolling processing method or the like.

As shown in FIG. 21B, each jig 33 is provided with a convex part 33 chaving a semicircular shape corresponding to the column-shaped narrowedpart 30 c, It is possible to form the column-shaped narrowed part 30 cby transferring the shape of the convex part 33 c to the wire rod 30 x.

FIG. 22 is an enlarged sectional view of a wiring substrate devicehaving the terminals 30 in accordance with the third exemplaryembodiment.

Meanwhile, in FIG. 22, the same elements as those described in the firstexemplary embodiment are denoted with the same reference numerals asthose in the first exemplary embodiment and the descriptions thereof areomitted.

The wiring substrate device is manufactured by performing the sameprocesses as FIGS. 10A to 11B of the first exemplary embodiment, and hasa structure where the wiring substrate 1 and the semiconductor device 20are connected to each other by the terminals 30.

In the third exemplary embodiment, the narrowed part 30 c is formed tohave a column shape, as described above. Therefore, it is possible tolargely retreat the surface of the narrowed part 30 c from a surface ofeach of the lower end 30 a and the upper end 30 b, and to largelyseparate the narrowed parts 30 c of the adjacent terminals 30. For thisreason, even when the solder 31 is reflowed in the process of FIG. 11B,it is possible to effectively suppress the adjacent terminals 30 frombeing connected each other due to the solder 31.

Also, even when the narrowed part 30 c is formed to have a column shape,following effects are accomplished, like the first exemplary embodiment.

FIGS. 23 and 24 are sectional views for illustrating effects to beaccomplished in the third exemplary embodiment.

FIG. 23 is a sectional view depicting a case where the heights of theplurality of electrodes 21 are not uniform due to a manufacturing error.

In this case, the narrowed parts 30 c are squashed, so that it ispossible to absorb the non-uniformity of the heights of the respectiveelectrodes 21 by the terminals 30 and to connect each of the pluralityof terminals 30 to the electrode 21.

FIG. 24 is a sectional view depicting a case where the semiconductordevice 20 is bent due to thermal expansion or the like.

In this case, the narrowed part 30 c is bent, so that the upper end 30 bof the terminal 30 conforms to the bending of the semiconductor device20 and it is thus possible to connect each of the plurality of terminals30 to the electrode 21.

Fourth Exemplary Embodiment

In the first to third exemplary embodiments, the semiconductor device 20is used as a component that is connected to the wiring substrate 1 viathe terminals 30. However, in a fourth exemplary embodiment, a wiringsubstrate is used as the component.

FIG. 25 is an enlarged sectional view of a wiring substrate device inaccordance with the fourth exemplary embodiment.

Meanwhile, in FIG. 25, the same elements as those described in the firstexemplary embodiment are denoted with the same reference numerals asthose in the first exemplary embodiment and the descriptions thereof areomitted.

As shown in FIG. 25, in a wiring substrate device 50, the two wiringsubstrates 1 are made to face each other. Then, the solders 31 arereflowed and melted, so that the wirings 7 of the wiring substrates 1are connected to each other via the terminals 30.

Since the terminal 30 is provided with the narrowed part 30 c, asdescribed above, the melted solder 31 is accumulated at the narrowedpart 30 c, so that it is possible to prevent the solder 31 fromspreading in the horizontal direction of the substrate. As a result, itis possible to suppress the adjacent terminals 30 from being connectedto each other due to the solder 31, so that it is possible to improvethe yield of the wiring substrate device 50.

What is claimed is:
 1. A wiring substrate device comprising: a wiringsubstrate; a plurality of terminals each of which is provided upright onthe wiring substrate and has a lower end, an upper end and a narrowedpart between the lower end and the upper end; and a plurality of solderseach of which has a melting point lower than the terminals and covers asurface of the corresponding terminal.
 2. The wiring substrate deviceaccording to claim 1, wherein the narrowed part has a narrow portionhaving a smallest width, as seen from a cross sectional view, andwherein a sectional shape of the terminal is thinned in a tapered shapefrom the lower end toward the narrow portion and the sectional shape ofthe terminal is widened in a tapered shape from the narrow portiontoward the upper end.
 3. The wiring substrate device according to claim2, wherein the wiring substrate comprises: a wiring connected to theterminals via the solders, and a solder resist layer formed on thewiring around the terminals, and wherein the narrow portion ispositioned above an upper surface of the solder resist layer.
 4. Thewiring substrate device according to claim 1, wherein a side surface ofeach of the terminals is formed with a plurality of grooves extendingfrom the lower end to the upper end.
 5. The wiling substrate deviceaccording to claim 1, wherein each of the terminals has: an upper platecomprising the upper end, a lower plate comprising the lower end, and acolumn-shaped part connecting the upper plate and the lower plate eachother, and wherein a width of the column-shaped part is constant.
 6. Thewiring substrate device according to claim 1, further comprising: acomponent connected to the terminals via the solders.
 7. The wiringsubstrate device according to claim 6, wherein the component is asemiconductor device or a separate wiring substrate from the wiringsubstrate.